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DATE
2006
IEEE
101views Hardware» more  DATE 2006»
16 years 24 days ago
A parallel configuration model for reducing the run-time reconfiguration overhead
Multitasking on reconfigurable logic can achieve very high silicon reusability. However, configuration latency is a major limitation and it can largely degrade the system performa...
Yang Qu, Juha-Pekka Soininen, Jari Nurmi
IPPS
2006
IEEE
16 years 23 days ago
Exploring the design space of an optimized compiler approach for mesh-like coarse-grained reconfigurable architectures
In this paper we study the performance improvements and trade-offs derived from an optimized mapping approach applied on a parametric coarse grained reconfigurable array architect...
Grigoris Dimitroulakos, Michalis D. Galanis, Const...
DAC
2006
ACM
16 years 21 days ago
Buffer memory optimization for video codec application modeled in Simulink
Reduction of the on-chip memory size is a key issue in video codec system design. Because video codec applications involve complex algorithms that are both data-intensive and cont...
Sang-Il Han, Xavier Guerin, Soo-Ik Chae, Ahmed Ami...
ISLPED
2006
ACM
73views Hardware» more  ISLPED 2006»
16 years 21 days ago
Substituting associative load queue with simple hash tables in out-of-order microprocessors
Buffering more in-flight instructions in an out-of-order microprocessor is a straightforward and effective method to help tolerate the long latencies generally associated with ...
Alok Garg, Fernando Castro, Michael C. Huang, Dani...
PPPJ
2006
ACM
16 years 21 days ago
Enabling Java mobile computing on the IBM Jikes research virtual machine
Today’s complex applications must face the distribution of data and code among different network nodes. Java is a wide-spread language that allows developers to build complex so...
Giacomo Cabri, Letizia Leonardi, Raffaele Quitadam...