3507 search results - page 379 / 702 » Slicing for architectural analysis |
171
click to vote
HPCA
2003
IEEE
16 years 8 months ago
2003
IEEE
Thread-level speculation provides architectural support to aggressively run hard-to-analyze code in parallel. As speculative tasks run concurrently, they generate unsafe or specul...
178
Voted
HPCA
2003
IEEE
16 years 8 months ago
2003
IEEE
Due to cost, time, and flexibility constraints, simulators are often used to explore the design space when developing a new processor architecture, as well as when evaluating the ...
181
Voted
DAC
2009
ACM
16 years 2 months ago
2009
ACM
The latest advancements in the commercial formal model checkers have enabled the integration of formal property verification with the conventional testbench based methods in the o...
203
Voted
IPPS
2008
IEEE
16 years 1 months ago
2008
IEEE
We present an auto-tuning approach to optimize application performance on emerging multicore architectures. The methodology extends the idea of searchbased performance optimizatio...
228
Voted
ISCA
2008
IEEE
16 years 1 months ago
2008
IEEE
As the number of cores per die increases, be they processors, memory blocks, or custom accelerators, the on-chip interconnect the cores use to communicate gains importance. We beg...