A physical yet compact gate delay model is developed integrating short-channel effects and the Alpha-power law based timing model. This analytical approach accurately predicts bot...
- Even though state-of-the-art FPGAs present new opportunities in exploring low-cost high-performance architectures for floating-point scientific applications, they also pose serio...
The integration among DW, OLAP and GIS has been given considerable attention in recent years by many researchers and industrial corporations. This may be a result of: 1) DW/OLAP ca...
Robson do Nascimento Fidalgo, Joel da Silva, Val&e...
We study diagnosis of segments on speedpaths that fail the timing constraint at the post-silicon stage due to manufacturing variations. We propose a formal procedure that is appli...
Given the resurgent attractiveness of single-instruction-multiple-data (SIMD) processing, it is important for high-performance computing applications to be SIMD-capable. The Hartr...
Tirath Ramdas, Gregory K. Egan, David Abramson, Ki...