3507 search results - page 442 / 702 » Slicing for architectural analysis |
215
click to vote
PLDI
1995
ACM
15 years 10 months ago
1995
ACM
Traditional list schedulers order instructions based on an optimistic estimate of the load latency imposed by the hardware and therefore cannot respond to variations in memory lat...
175
click to vote
DAC
2010
ACM
15 years 10 months ago
2010
ACM
With the end of clock-frequency scaling, parallelism has emerged as the key driver of chip-performance growth. Yet, several factors undermine efficient simultaneous use of onchip ...
163
click to vote
ASPDAC
2005
ACM
15 years 9 months ago
2005
ACM
- The increasing complexity of SoCs makes networks on chip (NoC) a promising substitute for busses and dedicated wires interconnection schemes. However, new tools need to be develo...
189
click to vote
DAC
2005
ACM
15 years 9 months ago
2005
ACM
This paper describes a novel technique called Embedded Test-bench Control (ETC), extensively used in the verification of Tensilica’s latest configurable processor. Conventional ...
200
click to vote
DAC
2005
ACM
15 years 9 months ago
2005
ACM
Grid-warping is a recent placement strategy based on a novel physical analogy: rather than move the gates to optimize their location, it elastically deforms a model of the 2-D chi...