Sciweavers

3507 search results - page 458 / 702
» Slicing for architectural analysis
Sort
View
DAC
1998
ACM
16 years 8 months ago
A Mixed Nodal-Mesh Formulation for Efficient Extraction and Passive Reduced-Order Modeling of 3D Interconnects
As VLSI circuit speeds have increased, reliable chip and system design can no longer be performed without accurate threedimensional interconnect models. In this paper, we describe...
Nuno Alexandre Marques, Mattan Kamon, Jacob White,...
DAC
2003
ACM
16 years 8 months ago
Optimizations for a simulator construction system supporting reusable components
Exploring a large portion of the microprocessor design space requires the rapid development of efficient simulators. While some systems support rapid model development through the...
David A. Penry, David I. August
DAC
2003
ACM
16 years 8 months ago
Implications of technology scaling on leakage reduction techniques
The impact of technology scaling on three run-time leakage reduction techniques (Input Vector Control, Body Bias Control and Power Supply Gating) is evaluated by determining limit...
Yuh-Fang Tsai, David Duarte, Narayanan Vijaykrishn...
DAC
2004
ACM
16 years 8 months ago
Large-scale full-wave simulation
We describe a new extraction tool, EMX (Electro-Magnetic eXtractor), for the analysis of RF, analog and high-speed digital circuits. EMX is a fast full-wave field solver. It incor...
Sharad Kapur, David E. Long
DAC
2004
ACM
16 years 8 months ago
Automatic generation of breakpoint hardware for silicon debug
Scan-based silicon debug is a technique that can be used to help find design errors in prototype silicon more quickly. One part of this technique involves the inclusion of breakpo...
Bart Vermeulen, Mohammad Zalfany Urfianto, Sandeep...