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IESS
2007
Springer
165views Hardware» more  IESS 2007»
16 years 1 months ago
Data Reuse Driven Memory and Network-On-Chip Co-Synthesis
NoCs present a possible communication infrastructure solution to deal with increased design complexity and shrinking time-to-market. The communication infrastructure is a signific...
Ilya Issenin, Nikil Dutt
ICPP
2006
IEEE
16 years 1 months ago
Parallel Algorithms for Evaluating Centrality Indices in Real-world Networks
This paper discusses fast parallel algorithms for evaluating several centrality indices frequently used in complex network analysis. These algorithms have been optimized to exploi...
David A. Bader, Kamesh Madduri
ICSM
2006
IEEE
16 years 1 months ago
Software Feature Understanding in an Industrial Setting
Software Engineers frequently need to locate and understand the code that implements a specific user feature of a large system. This paper reports on a study by Motorola Inc. and ...
Michael Jiang, Michael Groble, Sharon Simmons, Den...
RTAS
2005
IEEE
16 years 21 days ago
Bounding Worst-Case Data Cache Behavior by Analytically Deriving Cache Reference Patterns
While caches have become invaluable for higher-end architectures due to their ability to hide, in part, the gap between processor speed and memory access times, caches (and partic...
Harini Ramaprasad, Frank Mueller
ICFEM
2005
Springer
16 years 19 days ago
An Evidential Tool Bus
Abstract. Theorem provers, model checkers, static analyzers, test generators. . . all of these and many other kinds of formal methods tools can contribute to the analysis and devel...
John M. Rushby