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FPL
2004
Springer
164views Hardware» more  FPL 2004»
15 years 10 months ago
Dynamic Prefetching in the Virtual Memory Window of Portable Reconfigurable Coprocessors
Abstract. In Reconfigurable Systems-On-Chip (RSoCs), operating systems can primarily (1) manage the sharing of limited reconfigurable resources, and (2) support communication betwe...
Miljan Vuletic, Laura Pozzi, Paolo Ienne
FMCAD
2006
Springer
15 years 10 months ago
Design for Verification of the PCI-X Bus
The importance of re-usable Intellectual Properties (IPs) cores is increasing due to the growing complexity of today's system-on-chip and the need for rapid prototyping. In th...
Haja Moinudeen, Ali Habibi, Sofiène Tahar
HPCN
2000
Springer
15 years 10 months ago
An Analytical Model for a Class of Architectures under Master-Slave Paradigm
We build an analytical model for an application utilizing master-slave paradigm. In the model, only three architecture parameters are used: latency, bandwidth and flop rate. Instea...
Yasemin Yalçinkaya, Trond Steihaug
ICS
2000
Tsinghua U.
15 years 10 months ago
Push vs. pull: data movement for linked data structures
As the performance gap between the CPU and main memory continues to grow, techniques to hide memory latency are essential to deliver a high performance computer system. Prefetchin...
Chia-Lin Yang, Alvin R. Lebeck
MICRO
1995
IEEE
102views Hardware» more  MICRO 1995»
15 years 10 months ago
Zero-cycle loads: microarchitecture support for reducing load latency
Untolerated load instruction latencies often have a significant impact on overall program performance. As one means of mitigating this effect, we present an aggressive hardware-b...
Todd M. Austin, Gurindar S. Sohi
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