7055 search results - page 1275 / 1411 » Some New 4-Designs |
180
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ISCA
2008
IEEE
16 years 1 months ago
2008
IEEE
In a chip-multiprocessor (CMP) system, the DRAM system is shared among cores. In a shared DRAM system, requests from a thread can not only delay requests from other threads by cau...
159
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ISCA
2008
IEEE
16 years 1 months ago
2008
IEEE
Multicore processors have emerged as a powerful platform on which to efficiently exploit thread-level parallelism (TLP). However, due to Amdahl’s Law, such designs will be incr...
174
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MICRO
2008
IEEE
16 years 1 months ago
2008
IEEE
Existing DRAM controllers employ rigid, non-adaptive scheduling and buffer management policies when servicing prefetch requests. Some controllers treat prefetch requests the same ...
202
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WCNC
2008
IEEE
16 years 1 months ago
2008
IEEE
Abstract—Dynamic ad hoc networks are mobile ad hoc networks (MANETs) where network characteristics, such as network density and node mobility, change significantly over time and...
209
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3DIM
2007
IEEE
16 years 1 months ago
2007
IEEE
This paper presents a new registration algorithm of a 2D image and a 3D geometrical model, which is robust for initial registration errors, for reconstructing a realistic 3D model...