6366 search results - page 85 / 1274 » Statistical Performance Modeling and Optimization |
169
click to vote
ICCAD
1994
IEEE
15 years 10 months ago
1994
IEEE
We consider the problem of performance driven lookup-table (LUT) based technology mapping for FPGAs using a general delay model. In the general delay model, each interconnection e...
220
click to vote
CASES
2006
ACM
16 years 19 days ago
2006
ACM
Developing an optimizing compiler for a newly proposed architecture is extremely difficult when there is only a simulator of the machine available. Designing such a compiler requ...
153
click to vote
NIPS
2007
15 years 8 months ago
2007
Hierarchical penalization is a generic framework for incorporating prior information in the fitting of statistical models, when the explicative variables are organized in a hiera...
240
click to vote
NAA
2004
Springer
16 years 23 hour ago
2004
Springer
In this paper, we develop a probabilistic model for estimation of the numbers of cache misses during the sparse matrix-vector multiplication (for both general and symmetric matrice...
166
click to vote
ICIP
2004
IEEE
16 years 8 months ago
2004
IEEE
In the framework of a face verification system using local features and a Gaussian Mixture Model based classifier, we address the problem of non-frontal face verification (when on...