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DATE
2000
IEEE
142views Hardware» more  DATE 2000»
15 years 11 months ago
Power and Delay Reduction via Simultaneous Logic and Placement Optimization in FPGAs
Traditional FPGA design flows have treated logic synthesis and physical design as separate steps. With the recent advances in technology, the lack of information on the physical ...
Balakrishna Kumthekar, Fabio Somenzi
IPPS
2000
IEEE
15 years 11 months ago
Sorting on the OTIS-Mesh
In this paper we present sorting algorithms on the recently introduced N2 processor OTIS-Mesh, a network with diameter 4 p N , 3 consisting of N connected meshes of size p N  p N...
Andre Osterloh
IPPS
1999
IEEE
15 years 11 months ago
A Communication Latency Hiding Parallelization of a Traffic Flow Simulation
This work implements and analyses a highway traffic flow simulation based on continuum modeling of traffic dynamics. A traffic-flow simulation was developed and mapped onto a para...
Charles Michael Johnston, Anthony T. Chronopoulos
KBSE
1999
IEEE
15 years 11 months ago
An Integration of Deductive Retrieval into Deductive Synthesis
Deductive retrieval and deductive synthesis are two conceptually closely related software development methods which apply theorem proving techniques to support the construction of...
Bernd Fischer 0002, Jon Whittle
LICS
1996
IEEE
15 years 11 months ago
Reactive Modules
We present a formal model for concurrent systems. The model represents synchronous and asynchronous components in a uniform framework that supports compositional (assume-guarantee)...
Rajeev Alur, Thomas A. Henzinger