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174
Voted
ASPDAC
2004
ACM
112views Hardware» more  ASPDAC 2004»
16 years 13 days ago
Longest path selection for delay test under process variation
- Under manufacturing process variation, a path through a fault site is called longest for delay test if there exists a process condition under which the path has the maximum delay...
Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, We...
ICDM
2002
IEEE
133views Data Mining» more  ICDM 2002»
15 years 12 months ago
Estimating the number of segments in time series data using permutation tests
Segmentation is a popular technique for discovering structure in time series data. We address the largely open problem of estimating the number of segments that can be reliably di...
Kari Vasko, Hannu Toivonen
215
Voted
TCAD
2002
134views more  TCAD 2002»
15 years 6 months ago
Testing and diagnosis of interconnect faults in cluster-based FPGA architectures
As IC densities are increasing, cluster-based FPGA architectures are becoming the architecture of choice for major FPGA manufacturers. A cluster-based architecture is one in which...
Ian G. Harris, Russell Tessier
204
Voted
CCECE
2011
IEEE
14 years 7 months ago
Towards a portable, memory-efficient test system for Conducted Energy Weapons
We present a readily portable, memory-efficient performance test system (PTS) for Tasers. The proposed PTS has been developped for the most widely used Conducted Energy Weapons (...
Peyman Rahmati, David Dawson, Andy Adler
171
Voted
GD
2003
Springer
16 years 7 days ago
Radial Level Planarity Testing and Embedding in Linear Time
A graph with an ordered k-partition of the vertices is radial level planar if there is a strictly outward drawing on k concentric levels without crossings. Radial level planarity ...
Christian Bachmaier, Franz-Josef Brandenburg, Mich...