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DFT
1999
IEEE
114views VLSI» more  DFT 1999»
15 years 12 months ago
Yield Enhancement Considerations for a Single-Chip Multiprocessor System with Embedded DRAM
A programmable single-chip multiprocessor system for video coding has been developed. The system is implemented in a high-performance 0.25 m logic/embedded DRAM process. It integr...
Markus Rudack, Dirk Niggemeyer
ET
2010
98views more  ET 2010»
15 years 6 months ago
MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics
Abstract As technology scales down into the nanometer era, delay testing of modern chips has become more and more important. Tests for the path delay fault model are widely used to...
Stephan Eggersglüß, Görschwin Fey,...
ECCV
2008
Springer
16 years 9 months ago
Modeling and Recognition of Landmark Image Collections Using Iconic Scene Graphs
This paper presents an approach for modeling landmark sites such as the Statue of Liberty based on large-scale contaminated image collections gathered from the Internet. Our system...
Xiaowei Li, Changchang Wu, Christopher Zach, Svetl...
CSB
2002
IEEE
103views Bioinformatics» more  CSB 2002»
16 years 16 days ago
Protein-Based Analysis of Alternative Splicing in the Human Genome
Understanding the functional significance of alternative splicing and other mechanisms that generate RNA transcript diversity is an important challenge facing modern-day molecular...
Ann E. Loraine, Gregg A. Helt, Melissa S. Cline, M...
214
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ICCV
2011
IEEE
14 years 7 months ago
Discriminative Learning of Relaxed Hierarchy for Large-scale Visual Recognition
In the real visual world, the number of categories a classifier needs to discriminate is on the order of hundreds or thousands. For example, the SUN dataset [24] contains 899 sce...
Tianshi Gao, Daphne Koller