87 search results - page 11 / 18 » Synthesis of Testable RTL Designs |
194
Voted
FPL
2009
Springer
15 years 10 months ago
2009
Springer
High-Level Synthesis (HLS) is the field of transforming a high-level programming language, such as C, into a register transfer level(RTL) description of the design. In HLS, Binary...
159
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ISSS
1997
IEEE
15 years 10 months ago
1997
IEEE
This paper presents a novel source-level dynamic analysis methodology and tool for High-Level Synthesis (HLS). It not only for the first time enables HLS to offer source-level de...
157
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ACSD
2005
IEEE
16 years 2 days ago
2005
IEEE
Register Transfer Level (RTL) synthesis model which simplified the design of clocked circuits allowed design automation boost and VLSI progress for more than a decade. Shrinking t...
193
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ICCAD
2007
IEEE
15 years 10 months ago
2007
IEEE
This paper addresses the design of multi-mode architectures for digital signal processing applications. We present a dedicated design flow and its associated high-level synthesis t...
151
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ISSS
1995
IEEE
15 years 10 months ago
1995
IEEE
We present an integrated approach aimed at predicting layout area needed to implement a behavioral description for a given performance goal. Our approach is novel because: (1) it ...