5744 search results - page 278 / 1149 » System level design, a VHDL based approach |
210
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ICOIN
2001
Springer
15 years 11 months ago
2001
Springer
We propose a new approach to easily creating 3 0 geometric models. A technique called interactive evolutionary computation (IEC) is introduced to accelerate user’s invention and...
215
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ICCD
1999
IEEE
15 years 11 months ago
1999
IEEE
This research explores any potential for an on-chip cache compression which can reduce not only cache miss ratio but also miss penalty, if main memory is also managed in compresse...
232
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CASES
2007
ACM
15 years 11 months ago
2007
ACM
The key to increasing performance without a commensurate increase in power consumption in modern processors lies in increasing both parallelism and core specialization. Core speci...
234
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CASSIS
2005
Springer
16 years 26 days ago
2005
Springer
System software for deeply embedded devices has to cope with a broad variety of requirements and platforms, but especially with strict resource constraints. To compete against prop...
233
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LCTRTS
2010
Springer
16 years 2 months ago
2010
Springer
With increasingly more complex Multi-Processor Systems on Chip (MPSoC) and shortening time-to- market projections, Transaction Level Modeling and Platform Aware Design are seen as...