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» System level design, a VHDL based approach
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ISVLSI
2006
IEEE
89views VLSI» more  ISVLSI 2006»
16 years 20 days ago
System Exploration of SystemC Designs
Due to increasing design complexity new methodologies for system modeling have been established in VLSI CAD. The SystemC methodology gains a significant reduction of design cycle...
Christian Genz, Rolf Drechsler
SAMOS
2007
Springer
16 years 23 days ago
Towards Multi-application Workload Modeling in Sesame for System-Level Design Space Exploration
The Sesame modeling and simulation framework aims at early and thus efficient system-level design space exploration of embedded multimedia system architectures. So far, Sesame onl...
Mark Thompson, Andy D. Pimentel
VLSID
2002
IEEE
105views VLSI» more  VLSID 2002»
16 years 7 months ago
A Heuristic for Clock Selection in High-Level Synthesis
Clock selection has a significant impact on the performance and quality of designs in high-level synthesis. In most synthesis systems, a convenient value of the clock is chosen or...
J. Ramanujam, Sandeep Deshpande, Jinpyo Hong, Mahm...
ISSS
2002
IEEE
130views Hardware» more  ISSS 2002»
15 years 11 months ago
System-Level Modeling of a Network Switch SoC
We present the modeling of the high-level design of a next generation network switch from the perspective of a ComputerAided Design (CAD) team within the larger context of a desig...
Andrew S. Cassidy, Christopher P. Andrews, Donald ...
JSA
2007
142views more  JSA 2007»
15 years 6 months ago
Efficient FPGA hardware development: A multi-language approach
This paper presents a multi-language framework to FPGA hardware development which aims to satisfy the dual requirement of high level hardware design and efficient hardware impleme...
Khaled Benkrid, Abdsamad Benkrid, S. Belkacemi