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ISCA
2002
IEEE
115views Hardware» more  ISCA 2002»
16 years 2 days ago
SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery
We develop an availability solution, called SafetyNet, that uses a unified, lightweight checkpoint/recovery mechanism to support multiple long-latency fault detection schemes. At...
Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, ...
ISSS
2002
IEEE
142views Hardware» more  ISSS 2002»
16 years 2 days ago
Round-Robin Arbiter Design and Generation
In this paper, we introduce a Round–robin Arbiter Generator (RAG) tool. The RAG tool can generate a design for a Bus Arbiter (BA). The BA is able to handle the exact number of b...
Vincent John Mooney III, George F. Riley, Eung S. ...
MSE
2002
IEEE
119views Hardware» more  MSE 2002»
16 years 2 days ago
Narnia: A Virtual Machine for Multimedia Communication Services
Narnia is middleware that helps programmers build multimedia communication services. This middleware ollection of familiar programming abstractions— including events, event hand...
Mauricio Cortes, J. Robert Ensor
FPL
2009
Springer
99views Hardware» more  FPL 2009»
15 years 11 months ago
Exploiting fast carry-chains of FPGAs for designing compressor trees
Fast carry chains featuring dedicated adder circuitry is a distinctive feature of modern FPGAs. The carry chains bypass the general routing network and are embedded in the logic b...
Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
DATE
2000
IEEE
110views Hardware» more  DATE 2000»
15 years 11 months ago
Stochastic Modeling and Performance Evaluation for Digital Clock and Data Recovery Circuits
Clock and data recovery circuits are essential components in communication systems. They directly influence the bit-error-rate performance of communication links. It is desirable...
Alper Demir, Peter Feldmann