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ICCAD
1996
IEEE
127views Hardware» more  ICCAD 1996»
15 years 11 months ago
Comparing models of computation
We give a denotational framework (a "meta model") within which certain properties of models of computation can be understood and compared. It describes concurrent proces...
Edward A. Lee, Alberto L. Sangiovanni-Vincentelli
ICCAD
1996
IEEE
106views Hardware» more  ICCAD 1996»
15 years 11 months ago
Interchangeable pin routing with application to package layout
Many practical routing problems such as BGA, PGA, pin redistribution and test xture routing involve routing with interchangeable pins. These routing problems, especiallypackage la...
Man-Fai Yu, Joel Darnauer, Wayne Wei-Ming Dai
ICCD
1993
IEEE
90views Hardware» more  ICCD 1993»
15 years 11 months ago
Subterranean: A 600 Mbit/Sec Cryptographic VLSI Chip
In this paper the design of a high-speed cryptographic coprocessor is presented. This coprocessor is named Subterranean and can be used for both cryptographic pseudorandom sequenc...
Luc J. M. Claesen, Joan Daemen, Mark Genoe, G. Pee...
ISCAS
1994
IEEE
92views Hardware» more  ISCAS 1994»
15 years 11 months ago
A Study on the Stochastic Computation Using the Ratio of One Pulses and Zero Pulses
Stochastic computation uses pulse streams to represent numbers. In this paper, we have studied the novel method to implement the number system which uses the ratio of the number o...
Seung-Jai Min, Eel-Wan Lee, Soo-Ik Chae
179
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ASPDAC
2009
ACM
141views Hardware» more  ASPDAC 2009»
15 years 11 months ago
Adaptive inter-router links for low-power, area-efficient and reliable Network-on-Chip (NoC) architectures
Abstract-- The increasing wire delay constraints in deep submicron VLSI designs have led to the emergence of scalable and modular Network-on-Chip (NoC) architectures. As the power ...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri...