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192
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DATE
2004
IEEE
15 years 10 months ago
2004
IEEE
Latency-insensitive systems were recently proposed by Carloni et al. as a correct-by-construction methodology for single-clock system-on-a-chip (SoC) design using predesigned IP b...
172
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FPL
2004
Springer
15 years 10 months ago
2004
Springer
In this paper, we develop a unified theory in analyzing optimal switch box design problems, particularly for the unsolved irregular cases, where different pin counts are allowed on...
183
Voted
DATE
2006
IEEE
15 years 10 months ago
2006
IEEE
This paper presents the design of a Time-Triggered Ethernet (TTE) Switch, which is one of the core units of the Time-Triggered Ethernet system. Time-triggered Ethernet is a commun...
167
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FPL
2006
Springer
15 years 10 months ago
2006
Springer
In this paper we present the design and implementation of a dynamically reconfigurable system for packet queue scheduling. Two widely accepted queue schedulers have been implement...
162
Voted
ASPDAC
2001
ACM
15 years 10 months ago
2001
ACM
One of the most challenging issues in today's high-performance VLSI design is to ensure high-quality power supply to each individual circuit blocks. Reduced power supply volt...