Sciweavers

3340 search results - page 518 / 668
» Teaching networking hardware
Sort
View
ASAP
2008
IEEE
161views Hardware» more  ASAP 2008»
15 years 9 months ago
Configurable and scalable high throughput turbo decoder architecture for multiple 4G wireless standards
In this paper, we propose a novel multi-code turbo decoder architecture for 4G wireless systems. To support various 4G standards, a configurable multi-mode MAP (maximum a posterio...
Yang Sun, Yuming Zhu, Manish Goel, Joseph R. Caval...
ASPDAC
2008
ACM
108views Hardware» more  ASPDAC 2008»
15 years 9 months ago
Synthesis and design of parameter extractors for low-power pre-computation-based content-addressable memory using gate-block sel
Content addressable memory (CAM) is frequently used in applications, such as lookup tables, databases, associative computing, and networking, that require high-speed searches due t...
Jui-Yuan Hsieh, Shanq-Jang Ruan
ASPDAC
2008
ACM
151views Hardware» more  ASPDAC 2008»
15 years 9 months ago
High performance current-mode differential logic
This paper presents a new logic style, named Current-Mode Differential logic (CMDL), that achieves both high operating speed and low power consumption. Inspired by the low-voltage ...
Ling Zhang, Jianhua Liu, Haikun Zhu, Chung-Kuan Ch...
ASPDAC
2008
ACM
104views Hardware» more  ASPDAC 2008»
15 years 9 months ago
Low power clock buffer planning methodology in F-D placement for large scale circuit design
Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...
Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xian...
APCCAS
2006
IEEE
252views Hardware» more  APCCAS 2006»
15 years 9 months ago
A Display Order Oriented Scalable Video Decoder
As network technologies advance, Scalable Video Coding (SVC) has become increasingly popular due to its universal multimedia access capability and competitive compression performan...
Jia-Bin Huang, Yu-Kun Lin, Tian-Sheuan Chang