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ERSA
2010
172views Hardware» more  ERSA 2010»
15 years 5 months ago
A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics
Interconnect architecture is a primary research issue for emerging many-core processors. Packet switched Networks-on-Chip (NoCs) are considered key to success but since they delive...
Heiner Giefers, Marco Platzner
205
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MICRO
2010
IEEE
167views Hardware» more  MICRO 2010»
15 years 5 months ago
Erasing Core Boundaries for Robust and Configurable Performance
Single-thread performance, reliability and power efficiency are critical design challenges of future multicore systems. Although point solutions have been proposed to address thes...
Shantanu Gupta, Shuguang Feng, Amin Ansari, Scott ...
ASPDAC
2009
ACM
115views Hardware» more  ASPDAC 2009»
15 years 4 months ago
Frequent value compression in packet-based NoC architectures
The proliferation of Chip Multiprocessors (CMPs) has led to the integration of large on-chip caches. For scalability reasons, a large on-chip cache is often divided into smaller ba...
Ping Zhou, Bo Zhao, Yu Du, Yi Xu, Youtao Zhang, Ju...
JSAC
2011
115views more  JSAC 2011»
15 years 2 months ago
Scalable Cross-Layer Wireless Access Control Using Multi-Carrier Burst Contention
Abstract—The increasing demand for wireless access in vehicular environments (WAVE) supporting a wide range of applications such as traffic safety, surveying, infotainment etc.,...
Bogdan Roman, Ian J. Wassell, Ioannis Chatzigeorgi...
223
Voted
DATE
2010
IEEE
197views Hardware» more  DATE 2010»
15 years 2 months ago
Compilation of stream programs for multicore processors that incorporate scratchpad memories
The stream processing characteristics of many embedded system applications in multimedia and networking domains have led to the advent of stream based programming formats. Several ...
Weijia Che, Amrit Panda, Karam S. Chatha