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ASAP
2006
IEEE
111views Hardware» more  ASAP 2006»
16 years 1 months ago
Fast Bit Compression and Expansion with Parallel Extract and Parallel Deposit Instructions
Current microprocessor instruction set architectures are word oriented, with some subword support. Many important applications, however, can realize substantial performance benefi...
Yedidya Hilewitz, Ruby B. Lee
150
Voted
CRV
2006
IEEE
155views Robotics» more  CRV 2006»
16 years 1 months ago
Collaborative Multi-Camera Surveillance with Automated Person Detection
This paper presents the groundwork for a distributed network of collaborating, intelligent surveillance cameras, implemented with low-cost embedded microprocessor camera modules. ...
Trevor Ahmedali, James J. Clark
IJCNN
2006
IEEE
16 years 1 months ago
A Mobile Vision System with Reconfigurable Intelligent Agents
— Performing face detection and tracking on a mobile robot in a dynamic environment is a challenging task with the real-time constraints. To realize a natural reactive behavior o...
Yan Meng
ISCAS
2006
IEEE
157views Hardware» more  ISCAS 2006»
16 years 1 months ago
DCOS: cache embedded switch architecture for distributed shared memory multiprocessor SoCs
Abstract— Shared memory is a common inter-processor communication paradigm for on-chip multiprocessor SoC (MPSoC) platforms. The latency overhead of switch-based interconnection ...
Daewook Kim, Manho Kim, Gerald E. Sobelman
185
Voted
ISCAS
2006
IEEE
120views Hardware» more  ISCAS 2006»
16 years 1 months ago
Fast bit permutation unit for media enhanced microprocessors
— Bit and subword permutations are useful in many multimedia and cryptographic applications. New shift and permute instructions have been added to the instruction set of general-...
Giorgos Dimitrakopoulos, Christos Mavrokefalidis, ...