64 search results - page 8 / 13 » Test pattern generation for width compression in BIST |
155
Voted
VTS
2000
IEEE
15 years 10 months ago
2000
IEEE
We propose a novel BIST technique for non-scan sequential circuits which does not modify the circuit under test. It uses a learning algorithm to build a hardware test sequence gen...
147
Voted
ATS
2000
IEEE
15 years 10 months ago
2000
IEEE
We present a new pseudorandom testing algorithm for the Built-In Self-Test (BIST) of DRAM. In this algorithm, test patterns are complemented to generate state-transitions that are...
182
Voted
VLSID
2005
IEEE
15 years 12 months ago
2005
IEEE
During pseudorandom testing, a significant amount of energy and test application time is wasted for generating and for applying “useless” test vectors that do not contribute t...
164
Voted
VTS
1995
IEEE
15 years 10 months ago
1995
IEEE
This paper presents a new approach for on-chip test pattern generation. The set of test patterns generated by a pseudo-random pattern generator (e.g., an LFSR) is transformed into...
196
Voted
ATS
2005
IEEE
16 years 6 hour ago
2005
IEEE
Abstract—This paper presents a low transition test pattern generator, called LT-LFSR, to reduce average and peak power of a circuit during test by reducing the transitions within...