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SAFECOMP
2004
Springer
16 years 10 days ago
A Hybrid Testing Methodology for Railway Control Systems
Giuseppe De Nicola, Pasquale di Tommaso, Rosaria E...
ATS
2003
IEEE
84views Hardware» more  ATS 2003»
16 years 8 days ago
Test Time Minimization for Hybrid BIST of Core-Based Systems
Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, ...
ITC
2002
IEEE
97views Hardware» more  ITC 2002»
15 years 12 months ago
A Multi-Language Goal-Tree Based Functional Test Planning System
Rajneesh Mahajan, Ramesh Govindarajulu, J. R. Arms...
DATE
2000
IEEE
99views Hardware» more  DATE 2000»
15 years 11 months ago
CAS-BUS: A Scalable and Reconfigurable Test Access Mechanism for Systems on a Chip
Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki
129
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ICTAI
2000
IEEE
15 years 11 months ago
A genetic algorithm-based system for generating test programs for microprocessor IP cores
Fulvio Corno, Matteo Sonza Reorda, Giovanni Squill...