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» The Computational Complexity of Delay Management
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NCA
2006
IEEE
16 years 1 months ago
Full QoS Support with 2 VCs for Single-chip Switches
Current interconnection standards providing hardware support for quality of service (QoS) consider up to 16 virtual channels (VCs) for this purpose. However, most implementations ...
Alejandro Martínez, Francisco José A...
PDP
2006
IEEE
16 years 1 months ago
An O(n) Distributed Deadlock Resolution Algorithm
This paper shows a new distributed algorithm for deadlock detection and resolution under the single-resource request model that highly improves the complexity measurements of prev...
Manuel Prieto, Jesús E. Villadangos, Federi...
ISPAN
2005
IEEE
16 years 18 days ago
A Fast Noniterative Scheduler for Input-Queued Switches with Unbuffered Crossbars
Most high-end switches use an input-queued or a combined input- and output-queued architecture. The switch fabrics of these architectures commonly use an iterative scheduling syst...
Kevin F. Chen, Edwin Hsing-Mean Sha, S. Q. Zheng
IEEEPACT
2002
IEEE
15 years 12 months ago
Efficient Interconnects for Clustered Microarchitectures
Clustering is an effective microarchitectural technique for reducing the impact of wire delays, the complexity, and the power requirements of microprocessors. In this work, we inv...
Joan-Manuel Parcerisa, Julio Sahuquillo, Antonio G...
MOBIHOC
2000
ACM
15 years 11 months ago
DDR: distributed dynamic routing algorithm for mobile ad hoc networks
— This paper presents an alternative simple loop-free bandwidth-efficient distributed routing algorithm for mobile ad hoc networks, denoted as distributed dynamic routing (DDR)....
Navid Nikaein, Houda Labiod, Christian Bonnet