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» The Computational Complexity of Delay Management
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VLSID
2002
IEEE
136views VLSI» more  VLSID 2002»
16 years 7 months ago
Buffered Routing Tree Construction under Buffer Placement Blockages
Interconnect delay has become a critical factor in determining the performance of integrated circuits. Routing and buffering are powerful means of improving the circuit speed and ...
Wei Chen, Massoud Pedram, Premal Buch
SECON
2008
IEEE
16 years 1 months ago
Decentralized Tick Synchronization for Multi-Hop Medium Slotting in Wireless Ad Hoc Networks Using Black Bursts
—In this paper, we present Black Burst Synchronization (BBS)1 , a novel protocol for decentralized network-wide tick synchronization in wireless ad hoc networks, located at MAC l...
Reinhard Gotzhein, Thomas Kuhn
GLVLSI
2006
IEEE
165views VLSI» more  GLVLSI 2006»
16 years 1 months ago
Block alignment in 3D floorplan using layered TCG
In modern IC design, the number of long on-chip wires has been growing rapidly because of the increasing circuit complexity. Interconnect delay has dominated over gate delay as te...
Jill H. Y. Law, Evangeline F. Y. Young, Royce L. S...
VTC
2006
IEEE
101views Communications» more  VTC 2006»
16 years 1 months ago
A Virtual Slot Multiple Access for IEEE 802.15.3 High-Rate Wireless Personal Area Networks
—The IEEE 802.15.3 has introduced a type of time division multiple access (TDMA) which allocates the variable length of timeslot within a constant time interval. However, it need...
Do-Youn Hwang, Eui Hyeok Kwon, Jae-Sung Lim
ATS
2000
IEEE
134views Hardware» more  ATS 2000»
15 years 11 months ago
Fsimac: a fault simulator for asynchronous sequential circuits
At very high frequencies, the major potential of asynchronous circuits is absence of clock skew and, through that, better exploitation of relative timing relations. This paper pre...
Susmita Sur-Kolay, Marly Roncken, Ken S. Stevens, ...