Sciweavers

4190 search results - page 204 / 838
» The Cost of Design
Sort
View
RTS
2006
132views more  RTS 2006»
15 years 7 months ago
A framework for modular analysis and exploration of heterogeneous embedded systems
Abstract The increasing complexity of heterogeneous systems-on-chip, SoC, and distributed embedded systems makes system optimization and exploration a challenging task. Ideally, a ...
Arne Hamann, Marek Jersak, Kai Richter, Rolf Ernst
CHI
2008
ACM
16 years 7 months ago
Activity-based prototyping of ubicomp applications for long-lived, everyday human activities
We designed an activity-based prototyping process realized in the ActivityDesigner system that combines the theoretical framework of Activity-Centered Design with traditional iter...
Yang Li, James A. Landay
DAC
2005
ACM
15 years 9 months ago
A watermarking system for IP protection by a post layout incremental router
In this paper, we introduce a new watermarking system for IP protection on post-layout design phase. Firstly the copyright is encrypted by DES (Data Encryption Standard) and then ...
Tingyuan Nie, Tomoo Kisaka, Masahiko Toyonaga
GLVLSI
2003
IEEE
134views VLSI» more  GLVLSI 2003»
16 years 15 days ago
Modeling QCA for area minimization in logic synthesis
Concerned by the wall that Moore’s Law is expected to hit in the next decade, the integrated circuit community is turning to emerging nanotechnologies for continued device impro...
Nadine Gergel, Shana Craft, John Lach
ISVLSI
2007
IEEE
131views VLSI» more  ISVLSI 2007»
16 years 1 months ago
Improving the Quality of Bounded Model Checking by Means of Coverage Estimation
Formal verification has become an important step in circuit and system design. A prominent technique is Bounded Model Checking (BMC) which is widely used in industry. In BMC it i...
Ulrich Kühne, Daniel Große, Rolf Drechs...