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ICPR
2004
IEEE
16 years 8 months ago
FPGA based Real-Time Visual Servoing
Real-time image processing tasks not only require high computing power but also high data bandwidth. Though current processors excel in computing power, memory throughput is still...
Jörg Langwald, Mathias Nickl, Stefan Jör...
203
Voted
ISQED
2006
IEEE
153views Hardware» more  ISQED 2006»
16 years 1 months ago
Improving Transient Error Tolerance of Digital VLSI Circuits Using RObustness COmpiler (ROCO)
Due to aggressive technology scaling, VLSI circuits are becoming increasingly susceptible to transient errors caused by single-event-upsets (SEUs). In this paper, we introduce two...
Chong Zhao, Sujit Dey
189
Voted
CSREAESA
2006
15 years 8 months ago
Power Optimization of Interconnection Networks for Transport Triggered Architecture
Transport triggered architecture (TTA) has been shown to provide an efficient way to design application specific instruction set processors. However, the interconnection network of...
Xue-mi Zhao, Zhiying Wang
192
Voted
JOC
2011
79views more  JOC 2011»
14 years 10 months ago
Tweakable Block Ciphers
We propose a new cryptographic primitive, the “tweakable block cipher.” Such a cipher has not only the usual inputs—message and cryptographic key—but also a third input, th...
Moses Liskov, Ronald L. Rivest, David Wagner
ISCA
1996
IEEE
120views Hardware» more  ISCA 1996»
15 years 11 months ago
Missing the Memory Wall: The Case for Processor/Memory Integration
Current high performance computer systems use complex, large superscalar CPUs that interface to the main memory through a hierarchy of caches and interconnect systems. These CPU-c...
Ashley Saulsbury, Fong Pong, Andreas Nowatzyk