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ISPASS
2010
IEEE
16 years 1 months ago
Synthesizing memory-level parallelism aware miniature clones for SPEC CPU2006 and ImplantBench workloads
Abstract—We generate and provide miniature synthetic benchmark clones for modern workloads to solve two pre-silicon design challenges, namely: 1) huge simulation time (weeks to m...
Karthik Ganesan, Jungho Jo, Lizy K. John
CISIS
2009
IEEE
16 years 1 months ago
Multiple-Paths Search with Concurrent Thread Scheduling for Fast AND/OR Tree Search
This paper proposes a fast AND/OR tree search algorithm using a multiple-paths concurrent search method. Conventional heuristic AND/OR tree search algorithms expand nodes in only ...
Fumiyo Takano, Yoshitaka Maekawa, Hironori Kasahar...
C3S2E
2009
ACM
16 years 1 months ago
CPU, SMP and GPU implementations of Nohalo level 1, a fast co-convex antialiasing image resampler
This article introduces Nohalo level 1 (“Nohalo”), the simplest member of a family of image resamplers which straighten diagonal interfaces without adding noticeable nonlinear...
Nicolas Robidoux, Minglun Gong, John Cupitt, Adam ...
ISSTA
2009
ACM
16 years 1 months ago
Exception analysis and points-to analysis: better together
Exception analysis and points-to analysis are typically done in complete separation. Past algorithms for precise exception analysis (e.g., pairing throw clauses with catch stateme...
Martin Bravenboer, Yannis Smaragdakis
CGO
2008
IEEE
16 years 1 months ago
Prediction and trace compression of data access addresses through nested loop recognition
This paper describes an algorithm that takes a trace (i.e., a sequence of numbers or vectors of numbers) as input, and from that produces a sequence of loop nests that, when run, ...
Alain Ketterlin, Philippe Clauss