Reverse engineering methods produce different descriptions of software architectures. In this work we analyze and define the task of exploring and comparing these descriptions. ...
We present an analytical model relating FPGA architectural parameters to the routability of the FPGA. The inputs to the model include the channel width and connection and switch b...
This paper presents two novel and high performance hardware architectures, implemented in FPGA technology, for the KASUMI block cipher; this algorithm lies at the core of the conf...
In this paper, we propose PDRAM, a novel energy efficient main memory architecture based on phase change random access memory (PRAM) and DRAM. The paper explores the challenges i...
— A fully differential translinear 3-phase sinusoidal oscillator architecture is presented. The architecture is meant for BiCMOS implementation and uses only NPN devices, typical...
Dimitrios N. Loizos, Paul-Peter Sotiriadis, Gert C...