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SASP
2009
IEEE
170views Hardware» more  SASP 2009»
16 years 1 months ago
Parade: A versatile parallel architecture for accelerating pulse train clustering
— In this paper, we present Parade, a novel and flexible parallel architecture for the deinterleaving of combined pulsetrains. This is a commonly performed task in various areas ...
Amin Ansari, Dan Zhang, Scott A. Mahlke
CODES
2007
IEEE
16 years 1 months ago
Performance and resource optimization of NoC router architecture for master and slave IP cores
System-on-Chip architectures incorporate several IP cores with well defined master and slave characteristics in terms of on-chip communication. The paper presents a parameterized ...
Glenn Leary, Krishna Mehta, Karam S. Chatha
ISCAS
2005
IEEE
126views Hardware» more  ISCAS 2005»
16 years 19 days ago
Scheduling algorithm for partially parallel architecture of LDPC decoder by matrix permutation
— The fully parallel LDPC decoding architecture can achieve high decoding throughput, but it suffers from large hardware complexity caused by a large set of processing units and ...
In-Cheol Park, Se-Hyeon Kang
SAC
2005
ACM
16 years 19 days ago
Multi-coordination of mobile agents: a model and a component-based architecture
This paper proposes a model along with a reference software architecture enabling multi-coordination between distributed and mobile software agents. Multi-coordination allows agen...
Giancarlo Fortino, Wilma Russo
OOPSLA
2005
Springer
16 years 16 days ago
Using dependency models to manage complex software architecture
An approach to managing the architecture of large software systems is presented. Dependencies are extracted from the code by a conventional static analysis, and shown in a tabular...
Neeraj Sangal, Ev Jordan, Vineet Sinha, Daniel Jac...