Sciweavers

5247 search results - page 253 / 1050
» The Generalized A* Architecture
Sort
View
GLVLSI
2005
IEEE
186views VLSI» more  GLVLSI 2005»
16 years 27 days ago
An FPGA design of AES encryption circuit with 128-bit keys
This paper addresses a pipelined partial rolling (PPR) architecture for the AES encryption. The key technique is the PPR architecture, which is suitable for FPGA implementation. U...
Hui Qin, Tsutomu Sasao, Yukihiro Iguchi
CCS
2010
ACM
15 years 5 months ago
Platform-independent programs
Given a single program (i.e., bit string), one may assume that the program's behaviors can be determined by first identifying the native runtime architecture and then executi...
Sang Kil Cha, Brian Pak, David Brumley, Richard Ja...
OOPSLA
2010
Springer
15 years 5 months ago
Towards a tool-based development methodology for sense/compute/control applications
This poster presents a design language and a tool suite covering the development life-cycle of a Sense/Compute/Control (SCC) application. This language makes it possible to define...
Damien Cassou, Julien Bruneau, Julien Mercadal, Qu...
ANCS
2007
ACM
15 years 11 months ago
Frame-aggregated concurrent matching switch
Network operators need high-capacity router architectures that can offer scalability, provide throughput and performance guarantees, and maintain packet ordering. However, previou...
Bill Lin, Isaac Keslassy
IPPS
2008
IEEE
16 years 1 months ago
Faster matrix-vector multiplication on GeForce 8800GTX
Recently a GPU has acquired programmability to perform general purpose computation fast by running ten thousands of threads concurrently. This paper presents a new algorithm for d...
N. Fujimoto