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» The Generalized A* Architecture
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CODES
2004
IEEE
15 years 11 months ago
A loop accelerator for low power embedded VLIW processors
The high transistor density afforded by modern VLSI processes have enabled the design of embedded processors that use clustered execution units to deliver high levels of performan...
Binu K. Mathew, Al Davis
FPL
2008
Springer
153views Hardware» more  FPL 2008»
15 years 9 months ago
Exploring FPGA network on chip implementations across various application and network loads
Abstract-The network on chip will become a future general purpose interconnect for FPGAs much like today's standard OPB or PLB bus architectures. However, performance characte...
Graham Schelle, Dirk Grunwald
SIGCOMM
2010
ACM
15 years 7 months ago
c-Through: part-time optics in data centers
Data-intensive applications that operate on large volumes of data have motivated a fresh look at the design of data center networks. The first wave of proposals focused on designi...
Guohui Wang, David G. Andersen, Michael Kaminsky, ...
SIGARCH
2008
107views more  SIGARCH 2008»
15 years 7 months ago
A lightweight streaming layer for multicore execution
As multicore architectures gain widespread use, it becomes increasingly important to be able to harness their additional processing power to achieve higher performance. However, e...
David Zhang, Qiuyuan J. Li, Rodric Rabbah, Saman A...
CCR
2005
131views more  CCR 2005»
15 years 7 months ago
A clean slate 4D approach to network control and management
Today's data networks are surprisingly fragile and difficult to manage. We argue that the root of these problems lies in the complexity of the control and management planes--...
Albert G. Greenberg, Gísli Hjálmt&ya...