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» The Generalized A* Architecture
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DAC
2009
ACM
16 years 8 months ago
NoC topology synthesis for supporting shutdown of voltage islands in SoCs
In many Systems on Chips (SoCs), the cores are clustered in to voltage islands. When cores in an island are unused, the entire island can be shutdown to reduce the leakage power c...
Ciprian Seiculescu, Srinivasan Murali, Luca Benini...
DAC
2008
ACM
16 years 8 months ago
Cache modeling in probabilistic execution time analysis
Multimedia-dominated consumer electronics devices (such as cellular phone, digital camera, etc.) operate under soft real-time constraints. Overly pessimistic worst-case execution ...
Yun Liang, Tulika Mitra
DAC
2007
ACM
16 years 8 months ago
A Self-Tuning Configurable Cache
The memory hierarchy of a system can consume up to 50% of microprocessor system power. Previous work has shown that tuning a configurable cache to a particular application can red...
Ann Gordon-Ross, Frank Vahid
DAC
2002
ACM
16 years 8 months ago
Model design using hierarchical web-based libraries
Design tools can be profitably associated with libraries of reusable modeling components that will make the description and also the validation of the models much easier. Furtherm...
Fabrice Bernardi, Jean François Santucci
DAC
2002
ACM
16 years 8 months ago
An integer linear programming based approach for parallelizing applications in On-chip multiprocessors
With energy consumption becoming one of the first-class optimization parameters in computer system design, compilation techniques that consider performance and energy simultaneous...
Ismail Kadayif, Mahmut T. Kandemir, Ugur Sezer