Sciweavers

2424 search results - page 318 / 485
» The High Level Architecture for Simulations
Sort
View
AINA
2005
IEEE
16 years 21 days ago
3D-VOQ Switch Design and Evaluation
Input Buffered Switches with Virtual Output Queues(VOQ) design to avoid Head-Of-Line problems, is a primary design of switches that can be scalable to very high speeds. However, t...
Ding-Jyh Tsaur, Xian-Yang Lu, Chin-Chi Wu, Woei Li...
173
Voted
ISCAS
2005
IEEE
127views Hardware» more  ISCAS 2005»
16 years 20 days ago
Wire-driven microarchitectural design space exploration
— In this paper, we propose an interconnect-driven framework that performs an efficient and effective design space exploration for deep submicron processor architecture design. ...
Mongkol Ekpanyapong, Chinnakrishnan S. Ballapuram,...
197
Voted
OTM
2005
Springer
16 years 17 days ago
Event Broker Grids with Filtering, Aggregation, and Correlation for Wireless Sensor Data
Abstract. A significant increase in real world event monitoring capability with wireless sensor networks brought a new challenge to ubiquitous computing. To manage high volume and...
Eiko Yoneki
IFIP
2001
Springer
15 years 11 months ago
An Evolutionary Approach for Pareto-optimal Configurations in SOC Platforms
: One of the most important problems in SOC platforms design is that of defining strategies for tuning the parameters of a parameterized system so as to obtain the Pareto-optimal s...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
IPPS
1999
IEEE
15 years 11 months ago
NWCache: Optimizing Disk Accesses via an Optical Network/Write Cache Hybrid
In this paper we propose a simple extension to the I/O architecture of scalable multiprocessors that optimizes page swap-outs significantly. More specifically, we propose the use o...
Enrique V. Carrera, Ricardo Bianchini