3922 search results - page 353 / 785 » The IA-64 Architecture at Work |
214
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FPGA
2004
ACM
15 years 11 months ago
2004
ACM
This paper presents a new approach to timing optimization for FPGA designs, namely incremental physical resynthesis, to answer the challenge of effectively integrating logic and p...
214
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DAC
2006
ACM
15 years 11 months ago
2006
ACM
Statistical static timing analysis (SSTA) has been a popular research topic in recent years. A fundamental issue with applying SSTA in practice today is the lack of reliable and e...
198
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DSD
2006
IEEE
15 years 11 months ago
2006
IEEE
Abstract-- Networks-on-Chip will serve as the central integration platform in future complex SoC designs, composed of a large number of heterogeneous processing resources. Most res...
185
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ESAW
2006
Springer
15 years 11 months ago
2006
Springer
Ad hoc networks are a type of computational system whose members may fail to, or choose not to, comply with the laws governing their behaviour. We are investigating to what extent ...
177
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ANSS
2001
IEEE
15 years 11 months ago
2001
IEEE
In this work, we study the different buffering techniques used in the literature to solve the contention problem in A TM switching architectures. The objective of our study is to ...