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ICSE
2001
IEEE-ACM
15 years 11 months ago
JMOCHA: A Model Checking Tool that Exploits Design Structure
Mocha is a model checker based on the theme of exploiting design modularity: instead of manipulating unstructured state-transition graphs, it supports the hierarchical modeling fra...
Rajeev Alur, Luca de Alfaro, Radu Grosu, Thomas A....
FPGA
1997
ACM
127views FPGA» more  FPGA 1997»
15 years 11 months ago
General Modeling and Technology-Mapping Technique for LUT-Based FPGAs
We present a general approach to the FPGA technology mapping problem that applies to any logic block composed of lookup tables LUTs and can yield optimal solutions. The connecti...
Amit Chowdhary, John P. Hayes
ICC
2007
IEEE
104views Communications» more  ICC 2007»
16 years 1 months ago
A Novel Graph Model for Maximum Survivability in Mesh Networks under Multiple Generic Risks
— This paper investigates the path protection problem in mesh networks under multiple generic risks. Disjoint logical links may fail simultaneously if they share the same compone...
Qingya She, Xiaodong Huang, Jason P. Jue
KCAP
2005
ACM
16 years 24 days ago
Matching utterances to rich knowledge structures to acquire a model of the speaker's goal
An ultimate goal of AI is to build end-to-end systems that interpret natural language, reason over the resulting logical forms, and perform actions based on that reasoning. This r...
Peter Z. Yeh, Bruce W. Porter, Ken Barker
TACAS
2005
Springer
98views Algorithms» more  TACAS 2005»
16 years 21 days ago
Monte Carlo Model Checking
We present MC2 , what we believe to be the first randomized, Monte Carlo algorithm for temporal-logic model checking, the classical problem of deciding whether or not a property s...
Radu Grosu, Scott A. Smolka