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170
Voted
DATE
2008
IEEE
161views Hardware» more  DATE 2008»
16 years 1 months ago
Defeating classical Hardware Countermeasures: a new processing for Side Channel Analysis
In the field of the Side Channel Analysis, hardware distortions such as glitches and random frequency are classical countermeasures. A glitch influences the side channel amplitu...
Denis Réal, Cécile Canovas, Jessy Cl...
SIPS
2008
IEEE
16 years 1 months ago
Efficient mapping of advanced signal processing algorithms on multi-processor architectures
Modern microprocessor technology is migrating from simply increasing clock speeds on a single processor to placing multiple processors on a die to increase throughput and power pe...
Bhavana B. Manjunath, Aaron S. Williams, Chaitali ...
DATE
2007
IEEE
118views Hardware» more  DATE 2007»
16 years 1 months ago
Statistical model order reduction for interconnect circuits considering spatial correlations
In this paper, we propose a novel statistical model order reduction technique, called statistical spectrum model order reduction (SSMOR) method, which considers both intra-die and...
Jeffrey Fan, Ning Mi, Sheldon X.-D. Tan, Yici Cai,...
166
Voted
GLVLSI
2007
IEEE
189views VLSI» more  GLVLSI 2007»
16 years 1 months ago
Hardware-accelerated path-delay fault grading of functional test programs for processor-based systems
The path-delay fault simulation of functional tests on complex circuits such as current processor-based systems is a daunting task. The amount of computing power and memory needed...
Paolo Bernardi, Michelangelo Grosso, Matteo Sonza ...
IPPS
2007
IEEE
16 years 1 months ago
Fast SEU Detection and Correction in LUT Configuration Bits of SRAM-based FPGAs
1 FPGAs are an appealing solution for the space-based remote sensing applications. However, in a low-earth orbit, configuration bits of SRAM-based FPGAs are susceptible to single-e...
Hamid R. Zarandi, Seyed Ghassem Miremadi, Costas A...