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BROADNETS
2006
IEEE
16 years 1 months ago
A Statistical Approach to Anomaly Detection in Interdomain Routing
Abstract— A number of events such as hurricanes, earthquakes, power outages can cause large-scale failures in the Internet. These in turn cause anomalies in the interdomain routi...
Shivani Deshpande, Marina Thottan, Tin Kam Ho, Bip...
CODES
2006
IEEE
16 years 1 months ago
A bus architecture for crosstalk elimination in high performance processor design
In deep sub-micron technology, the crosstalk effect between adjacent wires has become an important issue, especially between long on-chip buses. This effect leads to the increas...
Wen-Wen Hsieh, Po-Yuan Chen, TingTing Hwang
DATE
2006
IEEE
109views Hardware» more  DATE 2006»
16 years 1 months ago
A methodology for mapping multiple use-cases onto networks on chips
A communication-centric design approach, Networks on Chips (NoCs), has emerged as the design paradigm for designing a scalable communication infrastructure for future Systems on C...
Srinivasan Murali, Martijn Coenen, Andrei Radulesc...
DATE
2006
IEEE
78views Hardware» more  DATE 2006»
16 years 1 months ago
STAX: statistical crosstalk target set compaction
This paper presents STAX, a crosstalk target set compaction framework to reduce the complexity of the crosstalk ATPG process by pruning non-fault-producing targets. In general, ex...
Shahin Nazarian, Massoud Pedram, Sandeep K. Gupta,...
DFT
2006
IEEE
143views VLSI» more  DFT 2006»
16 years 1 months ago
Defect Tolerant and Energy Economized DSP Plane of a 3-D Heterogeneous SoC
This paper1 discusses a defect tolerant and energy economized computing array for the DSP plane of a 3-D Heterogeneous System on a Chip. We present the J-platform, which employs c...
Vijay K. Jain, Glenn H. Chapman