Sciweavers

1728 search results - page 144 / 346
» The Size of Power Automata
Sort
View
ISCAS
2006
IEEE
108views Hardware» more  ISCAS 2006»
16 years 1 months ago
Design methodology for global resonant H-tree clock distribution networks
Abstract—Design guidelines for resonant H-tree clock distribution networks are presented in this paper. A distributed model of a two-level resonant H-tree structure is described,...
Jonathan Rosenfeld, Eby G. Friedman
RTCSA
2005
IEEE
16 years 18 days ago
LyraNET: A Zero-Copy TCP/IP Protocol Stack for Embedded Operating Systems
Embedded systems are usually resource limited in terms of processing power, memory, and power consumption, thus embedded TCP/IP should be designed to make the best use of limited ...
Yun-Chen Li, Mei-Ling Chiang
CASES
2003
ACM
16 years 8 days ago
Frequent loop detection using efficient non-intrusive on-chip hardware
Dynamic software optimization methods are becoming increasingly popular for improving software performance and power. The first step in dynamic optimization consists of detecting ...
Ann Gordon-Ross, Frank Vahid
200
Voted
DATE
2010
IEEE
180views Hardware» more  DATE 2010»
16 years 3 days ago
A reconfigurable cache memory with heterogeneous banks
Abstract— The optimal size of a large on-chip cache can be different for different programs: at some point, the reduction of cache misses achieved when increasing cache size hits...
Domingo Benitez, Juan C. Moure, Dolores Rexachs, E...
179
Voted
MONET
2006
157views more  MONET 2006»
15 years 7 months ago
Connectivity in Wireless Ad-hoc Networks with a Log-normal Radio Model
In this paper we study connectivity in wireless ad-hoc networks by modeling the network as an undirected geometric random graph. The novel aspect in our study is that for finding t...
Ramin Hekmat, Piet Van Mieghem