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MICRO
2005
IEEE
145views Hardware» more  MICRO 2005»
16 years 1 months ago
A Mechanism for Online Diagnosis of Hard Faults in Microprocessors
We develop a microprocessor design that tolerates hard faults, including fabrication defects and in-field faults, by leveraging existing microprocessor redundancy. To do this, we...
Fred A. Bower, Daniel J. Sorin, Sule Ozev
172
Voted
MSS
2005
IEEE
97views Hardware» more  MSS 2005»
16 years 1 months ago
Richer File System Metadata Using Links and Attributes
Traditional file systems provide a weak and inadequate structure for meaningful representations of file interrelationships and other context-providing metadata. Existing designs...
Alexander Ames, Carlos Maltzahn, Nikhil Bobb, Etha...
208
Voted
PRDC
2005
IEEE
16 years 1 months ago
Partitioned Cache Shadowing for Deep Sub-Micron (DSM) Regime
An important issue in modern cache designs is bridging the gap between wire and device delays. This warrants the use of more regular and modular structures to mask wire latencies....
Heng Xu, Arun K. Somani
166
Voted
SBACPAD
2005
IEEE
139views Hardware» more  SBACPAD 2005»
16 years 1 months ago
Chained In-Order/Out-of-Order DoubleCore Architecture
Complexity is one of the most important problems facing microarchitects. It is exacerbated by the application of optimizations, by scaling to higher issue widths and, in general, ...
Miquel Pericàs, Adrián Cristal, Rube...
ACMMSP
2005
ACM
106views Hardware» more  ACMMSP 2005»
16 years 1 months ago
Impact of modern memory subsystems on cache optimizations for stencil computations
In this work we investigate the impact of evolving memory system features, such as large on-chip caches, automatic prefetch, and the growing distance to main memory on 3D stencil ...
Shoaib Kamil, Parry Husbands, Leonid Oliker, John ...
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