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» The Structure and Performance of Interpreters
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DCC
2003
IEEE
16 years 27 days ago
Universal Multiple Description Scalar Quantization: Analysis and Design
—This paper introduces a new high-rate analysis of the multiple description scalar quantizer (MDSQ) with balanced descriptions. The analysis provides insight into the structure o...
Chao Tian, Sheila S. Hemami
DSN
2003
IEEE
16 years 27 days ago
Evaluation of Fault Handling of the Time-Triggered Architecture with Bus and Star Topology
Arbitrary faults of a single node in a time-triggered architecture (TTA) bus topology system may cause error propagation to correct nodes and may lead to inconsistent system state...
Astrit Ademaj, Håkan Sivencrona, Günthe...
FTDCS
2003
IEEE
16 years 27 days ago
Distributed Shared State
Increasingly, Internet-level distributed systems are oriented as much toward information access as they are toward computation. From computer-supported collaborative work to peer-...
Michael L. Scott, DeQing Chen, Sandhya Dwarkadas, ...
GLVLSI
2003
IEEE
140views VLSI» more  GLVLSI 2003»
16 years 27 days ago
Exploiting multiple functionality for nano-scale reconfigurable systems
It is likely that it will become increasingly difficult to manufacture the complex, heterogeneous logic structures that characterise current reconfigurable logic systems. As a res...
Paul Beckett
GLVLSI
2003
IEEE
130views VLSI» more  GLVLSI 2003»
16 years 27 days ago
Mixing ATPG and property checking for testing HW/SW interfaces
A critical part of the design of HW/SW systems concerns the definition of the HW/SW interface. Such interfaces do not directly map a functionality of the system description, but ...
Alessandro Fin, Franco Fummi, Graziano Pravadelli
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