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» The Structure and Performance of Interpreters
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ICCAD
2005
IEEE
127views Hardware» more  ICCAD 2005»
16 years 4 months ago
Hardware synthesis from guarded atomic actions with performance specifications
We present a new hardware synthesis methodology for guarded atomic actions (or rules), which satisfies performance-related scheduling specifications provided by the designer. The ...
Daniel L. Rosenband
IEEEPACT
2009
IEEE
16 years 2 months ago
Soft-OLP: Improving Hardware Cache Performance through Software-Controlled Object-Level Partitioning
—Performance degradation of memory-intensive programs caused by the LRU policy’s inability to handle weaklocality data accesses in the last level cache is increasingly serious ...
Qingda Lu, Jiang Lin, Xiaoning Ding, Zhao Zhang, X...
SSDBM
2006
IEEE
163views Database» more  SSDBM 2006»
16 years 1 months ago
ACache: Using Caching to Improve the Performance of Multiple Sequence Alignments
Multiple sequence alignment represents a class of powerful bioinformatics tools with many uses in computational biology ranging from discovery of characteristic motifs and conserv...
Xun Tu, Kajal T. Claypool, Cindy X. Chen
IPTPS
2005
Springer
16 years 1 months ago
Clustering in P2P Exchanges and Consequences on Performances
— We propose here an analysis of a rich dataset which gives an exhaustive and dynamic view of the exchanges processed in a running eDonkey system. We focus on correlation in term...
Stevens Le-Blond, Jean-Loup Guillaume, Matthieu La...
ISPASS
2003
IEEE
16 years 24 days ago
Performance study of a cluster runtime system for dynamic interactive stream-oriented applications
Emerging application domains such as interactive vision, animation, and multimedia collaboration display dynamic scalable parallelism, and high computational requirements, making ...
Arnab Paul, Nissim Harel, Sameer Adhikari, Bikash ...