9059 search results - page 230 / 1812 » The design of eco-feedback technology |
196
click to vote
FPGA
2008
ACM
15 years 8 months ago
2008
ACM
Logical effort (LE) is a linear technique for modelling the delay of a circuit in a technology independent manner. It offers the potential to simplify delay models for FPGAs and g...
187
click to vote
CORR
2007
Springer
15 years 7 months ago
2007
Springer
: New nanotechnology based devices are replacing CMOS devices to overcome CMOS technology’s scaling limitations. However, many such devices exhibit nonmonotonic I-V characteristi...
167
click to vote
HPCA
2009
IEEE
16 years 7 months ago
2009
IEEE
Interconnection plays an important role in performance and power of CMP designs using deep sub-micron technology. The network-on-chip (NoCs) has been proposed as a scalable and hi...
185
click to vote
DATE
2009
IEEE
16 years 2 months ago
2009
IEEE
– The quest for technologies with superior device characteristics has showcased Carbon Nanotube Field Effect Transistors (CNFETs) into limelight. Among the several design aspects...
159
click to vote
DSD
2009
IEEE
16 years 2 months ago
2009
IEEE
— 3D stacked architectures provide significant benefits in performance, footprint and yield. However, vertical stacking increases the thermal resistances, and exacerbates tempe...