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DATE
2008
IEEE
120views Hardware» more  DATE 2008»
16 years 1 months ago
A Case Study in Reliability-Aware Design: A Resilient LDPC Code Decoder
Chip reliability becomes a great threat to the design of future microelectronic systems with the continuation of the progressive downscaling of CMOS technologies. Hence increasing...
Matthias May, Matthias Alles, Norbert Wehn
GLVLSI
2008
IEEE
128views VLSI» more  GLVLSI 2008»
16 years 1 months ago
NBTI-aware flip-flop characterization and design
With the scaling down of the CMOS technologies, Negative Bias Temperature Instability (NBTI) has become a major concern due to its impact on PMOS transistor aging process and the ...
Hamed Abrishami, Safar Hatami, Behnam Amelifard, M...
IV
2008
IEEE
89views Visualization» more  IV 2008»
16 years 1 months ago
A Practical Way for Projects to Visualize Design Rationale
Design rationale remains poorly explained and rarely modelled on projects in industry. However, the reasons for design decisions are important when a specification has to be re-ex...
Ian Alexander
MICRO
2008
IEEE
142views Hardware» more  MICRO 2008»
16 years 1 months ago
NBTI tolerant microarchitecture design in the presence of process variation
—Negative bias temperature instability (NBTI), which reduces the lifetime of PMOS transistors, is becoming a growing reliability concern for sub-micrometer CMOS technologies. Par...
Xin Fu, Tao Li, José A. B. Fortes
ISCAS
2007
IEEE
144views Hardware» more  ISCAS 2007»
16 years 1 months ago
Quasi-Resonant Interconnects: A Low Power Design Methodology
— Design and analysis guidelines for resonant interconnect networks are presented in this paper. The methodology focuses on developing an accurate analytic distributed model of t...
Jonathan Rosenfeld, Eby G. Friedman