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185
Voted
MSS
2011
IEEE
15 years 2 months ago
2011
IEEE
197
Voted
ISQED
2007
IEEE
16 years 1 months ago
2007
IEEE
In high-level synthesis for FPGA designs, scheduling and chaining of operations for optimal performance remain challenging problems. In this paper, we present a balanced schedulin...
173
Voted
ASPDAC
1999
ACM
15 years 11 months ago
1999
ACM
In this paper, we present a fast and efficient Iterative Improvement Partitioning (IIP) technique for VLSI circuits and hybrid bucket structures on its implementation. Due to thei...
138
Voted
ISCAS
2005
IEEE
16 years 1 months ago
2005
IEEE
— Compared with a single level Hamming associative memory, a simple model based on uniform random noise analysis has proved a twolevel decoupled Hamming network to be an efficie...
165
Voted
HOST
2008
IEEE
16 years 1 months ago
2008
IEEE
—Masking is a side-channel countermeasure that randomizes side-channel leakage, such as the power dissipation of a circuit. Masking is only effective on the condition that the in...