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DAC
2007
ACM
16 years 7 months ago
Characterization and Estimation of Circuit Reliability Degradation under NBTI using On-Line IDDQ Measurement
Negative bias temperature instability (NBTI) in MOSFETs is one of the major reliability challenges in nano-scale technology. This paper presents an efficient technique to characte...
Kunhyuk Kang, Kee-Jong Kim, Ahmad E. Islam, Muhamm...
FAST
2011
14 years 10 months ago
Leveraging Value Locality in Optimizing NAND Flash-based SSDs
: NAND flash-based solid-state drives (SSDs) are increasingly being deployed in storage systems at different levels such as buffer-caches and even secondary storage. However, the ...
Aayush Gupta, Raghav Pisolkar, Bhuvan Urgaonkar, A...
CF
2010
ACM
15 years 11 months ago
Interval-based models for run-time DVFS orchestration in superscalar processors
We develop two simple interval-based models for dynamic superscalar processors. These models allow us to: i) predict with great accuracy performance and power consumption under va...
Georgios Keramidas, Vasileios Spiliopoulos, Stefan...
CJ
2006
84views more  CJ 2006»
15 years 6 months ago
Instruction Level Parallelism through Microthreading - A Scalable Approach to Chip Multiprocessors
Most microprocessor chips today use an out-of-order instruction execution mechanism. This mechanism allows superscalar processors to extract reasonably high levels of instruction ...
Kostas Bousias, Nabil Hasasneh, Chris R. Jesshope
DSN
2009
IEEE
16 years 1 months ago
Low overhead Soft Error Mitigation techniques for high-performance and aggressive systems
The threat of soft error induced system failure in high performance computing systems has become more prominent, as we adopt ultra-deep submicron process technologies. In this pap...
Naga Durga Prasad Avirneni, Viswanathan Subramania...