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DATE
2002
IEEE
84views Hardware» more  DATE 2002»
16 years 17 days ago
Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications
Microprocessors are today getting more and more inefficient for a growing range of applications. Its principles -The Von Neumann paradigm[3]- based on the sequential execution of ...
Gilles Sassatelli, Lionel Torres, Pascal Benoit, T...
EUROPAR
2009
Springer
15 years 11 months ago
StarPU: A Unified Platform for Task Scheduling on Heterogeneous Multicore Architectures
Abstract. In the field of HPC, the current hardware trend is to design multiprocessor architectures that feature heterogeneous technologies such as specialized coprocessors (e.g., ...
Cédric Augonnet, Samuel Thibault, Raymond N...
ADBIS
1995
Springer
155views Database» more  ADBIS 1995»
15 years 11 months ago
The MaStA I/O Cost Model and its Validation Strategy
Crash recovery in database systems aims to provide an acceptable level of protection from failure at a given engineering cost. A large number of recovery mechanisms are known, and...
S. Scheuerl, Richard C. H. Connor, Ronald Morrison...
ICS
2010
Tsinghua U.
15 years 10 months ago
Clustering performance data efficiently at massive scales
Existing supercomputers have hundreds of thousands of processor cores, and future systems may have hundreds of millions. Developers need detailed performance measurements to tune ...
Todd Gamblin, Bronis R. de Supinski, Martin Schulz...
AAAI
2007
15 years 10 months ago
Using AI for e-Government Automatic Assessment of Immigration Application Forms
This paper describes an e-Government AI project that provides a range of intelligent AI services to support automated assessment of various types of applications submitted to an i...
Andy Hon Wai Chun
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