State of the art statistical timing analysis (STA) tools often yield less accurate results when timing variables become correlated. Spatial correlation and correlation caused by p...
This paper proposes applying a logic synthesis approach to high level synthesis from SpecC specifications to timed asynchronous gate-level circuits. The state-based logic synthes...
: In this paper we rst present a general lower bound on the stabilization time which holds for a number of graph theoretic problems, including leader election, spanning tree constr...
Abstract. Temporal logic is popular for specifying correctness properties of reactive systems. Real-time temporal logics add the ability to express quantitative timing aspects. Tab...
This paper considers an M/G/1 queue in which service time distributions in each busy period change according to a finite state Markov chain, embedded at the arrival instants of cu...