40 search results - page 1 / 8 » Timing Driven Placement for Large Standard Cell Circuits |
125
Voted
DAC
1995
ACM
15 years 10 months ago
1995
ACM
183
Voted
ICCD
1997
IEEE
15 years 10 months ago
1997
IEEE
Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a compute-intensive process. All previous work in parallel simulated annealing bas...
171
click to vote
ICCAD
2000
IEEE
15 years 10 months ago
2000
IEEE
In this paper, we develop a new standard cell placement tool, Dragon2000, to solve large scale placement problem effectively. A top-down hierarchical approach is used in Dragon200...
172
click to vote
GLVLSI
2000
IEEE
15 years 10 months ago
2000
IEEE
We present a new timing driven method for global placement. Our method is based on the observation that similar net length reductions in the different nets that make up a path may...
147
Voted
ICCAD
2001
IEEE
16 years 3 months ago
2001
IEEE
Retiming is a widely investigated technique for performance optimization. It performs powerful modifications on a circuit netlist. However, often it is not clear, whether the pred...