204 search results - page 20 / 41 » Trace Processors |
156
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MICRO
2000
IEEE
15 years 6 months ago
2000
IEEE
This paper demonstrates how an Instruction Path Coprocessor (I-COP) can be efficiently implemented using the PipeRench reconfigurable architecture. An I-COP is a programmable on-c...
177
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LCPC
2007
Springer
16 years 18 days ago
2007
Springer
Recent studies have shown that programming in a Partition Global Address Space (PGAS) language can be more productive than programming in a message passing model. One reason for th...
191
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IEEEPACT
2007
IEEE
16 years 23 days ago
2007
IEEE
Nowadays, multithreaded architectures are becoming more and more popular. In order to evaluate their behavior, several methodologies and metrics have been proposed. A methodology ...
181
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ICCS
2009
Springer
16 years 1 months ago
2009
Springer
Abstract. Contemporary high-end Terascale and Petascale systems are composed of hundreds of thousands of commodity multi-core processors interconnected with high-speed custom netwo...
168
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ISPDC
2008
IEEE
16 years 26 days ago
2008
IEEE
We present a load-balancing technique that exploits the temporal coherence, among successive computation phases, in mesh-like computations to be mapped on a cluster of processors....